34 #define QQQdialect MPLABX 48 #undef QQQMULTIPROCESSEXH 51 #define qqqMaxBranchDepth 20 52 #define QQQstructbitmap 64 #undef QQQTEMPLATEONLY 66 #define QQQUPLOADATEND 68 #undef QQQASHLINGVITRA 70 #define qqqbitmapint unsigned int 72 #undef QQQTIC2XSERIALIO 74 #undef QQQCOMPRESSED_EXH 81 #define app_64zzopen zzopen 83 #define app_64zqqzqz1 zqqzqz1 86 #define FILEPOINT FILE * f, 87 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 107 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 108 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 116 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 117 #ifndef LDRA_VOID_FUNC 118 #define LDRA_VOID_FUNC 121 #if defined(QQQMAINFL) 144 #ifdef QQQ_KEEPCOMMENTS 152 #if !defined(QQQSUPPRESS_UNDEF) 158 #undef QQQHITMAP_STORAGE 160 #define qqnull_params void 161 #define QQQ_PROTOTYPE_DEF 163 #undef QQ_ANSI_PROTOTYPE 165 #define QQ_ANSI_PROTOTYPE 1 168 #define QQ_ANSI_PROTOTYPE 1 174 #define ELEMENT(N) qqqbitmapint element##N; 176 #include "app_64zbelem.def" 180 #define ELEMENT(N) 0, 182 #include "app_64zbelem.def" 236 #ifndef _SYSTEM_CONFIG_H 237 #define _SYSTEM_CONFIG_H 256 #define SYS_VERSION_STR "2.06" 257 #define SYS_VERSION 20600 261 #define SYS_CLK_FREQ 200000000ul 262 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 263 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 264 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 265 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 266 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 267 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 268 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 269 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 270 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 272 #define SYS_PORT_A_ANSEL 0x3F00 273 #define SYS_PORT_A_TRIS 0xFFED 274 #define SYS_PORT_A_LAT 0x0010 275 #define SYS_PORT_A_ODC 0x0000 276 #define SYS_PORT_A_CNPU 0x0020 277 #define SYS_PORT_A_CNPD 0x0000 278 #define SYS_PORT_A_CNEN 0x0021 279 #define SYS_PORT_B_ANSEL 0x10C8 280 #define SYS_PORT_B_TRIS 0x91FF 281 #define SYS_PORT_B_LAT 0x0000 282 #define SYS_PORT_B_ODC 0x0000 283 #define SYS_PORT_B_CNPU 0x0000 284 #define SYS_PORT_B_CNPD 0x0000 285 #define SYS_PORT_B_CNEN 0x0000 286 #define SYS_PORT_C_ANSEL 0xCFE1 287 #define SYS_PORT_C_TRIS 0xFFFF 288 #define SYS_PORT_C_LAT 0x0000 289 #define SYS_PORT_C_ODC 0x0000 290 #define SYS_PORT_C_CNPU 0x0000 291 #define SYS_PORT_C_CNPD 0x0000 292 #define SYS_PORT_C_CNEN 0x0000 293 #define SYS_PORT_D_ANSEL 0xC100 294 #define SYS_PORT_D_TRIS 0xFFFF 295 #define SYS_PORT_D_LAT 0x0000 296 #define SYS_PORT_D_ODC 0x0000 297 #define SYS_PORT_D_CNPU 0x0000 298 #define SYS_PORT_D_CNPD 0x0000 299 #define SYS_PORT_D_CNEN 0x0000 300 #define SYS_PORT_E_ANSEL 0xFC00 301 #define SYS_PORT_E_TRIS 0xFDFF 302 #define SYS_PORT_E_LAT 0x0000 303 #define SYS_PORT_E_ODC 0x0000 304 #define SYS_PORT_E_CNPU 0x0000 305 #define SYS_PORT_E_CNPD 0x0000 306 #define SYS_PORT_E_CNEN 0x0000 307 #define SYS_PORT_F_ANSEL 0xCEC0 308 #define SYS_PORT_F_TRIS 0xEFFF 309 #define SYS_PORT_F_LAT 0x0000 310 #define SYS_PORT_F_ODC 0x0000 311 #define SYS_PORT_F_CNPU 0x0000 312 #define SYS_PORT_F_CNPD 0x0000 313 #define SYS_PORT_F_CNEN 0x0000 314 #define SYS_PORT_G_ANSEL 0x8CBC 315 #define SYS_PORT_G_TRIS 0xDFFF 316 #define SYS_PORT_G_LAT 0x0000 317 #define SYS_PORT_G_ODC 0x0000 318 #define SYS_PORT_G_CNPU 0x0000 319 #define SYS_PORT_G_CNPD 0x0000 320 #define SYS_PORT_G_CNEN 0x0000 321 #define SYS_PORT_H_ANSEL 0x0070 322 #define SYS_PORT_H_TRIS 0xB3FB 323 #define SYS_PORT_H_LAT 0x0000 324 #define SYS_PORT_H_ODC 0x0000 325 #define SYS_PORT_H_CNPU 0x0000 326 #define SYS_PORT_H_CNPD 0x0000 327 #define SYS_PORT_H_CNEN 0x0000 328 #define SYS_PORT_J_ANSEL 0x0000 329 #define SYS_PORT_J_TRIS 0x8B7F 330 #define SYS_PORT_J_LAT 0x0080 331 #define SYS_PORT_J_ODC 0x0000 332 #define SYS_PORT_J_CNPU 0x0000 333 #define SYS_PORT_J_CNPD 0x0000 334 #define SYS_PORT_J_CNEN 0x0800 335 #define SYS_PORT_K_ANSEL 0xFF00 336 #define SYS_PORT_K_TRIS 0xFFFF 337 #define SYS_PORT_K_LAT 0x0000 338 #define SYS_PORT_K_ODC 0x0000 339 #define SYS_PORT_K_CNPU 0x0000 340 #define SYS_PORT_K_CNPD 0x0000 341 #define SYS_PORT_K_CNEN 0x0000 345 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 346 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 347 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 348 #define SYS_TMR_FREQUENCY 1000 349 #define SYS_TMR_FREQUENCY_TOLERANCE 10 350 #define SYS_TMR_UNIT_RESOLUTION 10000 351 #define SYS_TMR_CLIENT_TOLERANCE 10 352 #define SYS_TMR_INTERRUPT_NOTIFICATION false 358 #define DRV_IC_DRIVER_MODE_STATIC 361 #define DRV_SPI_NUMBER_OF_MODULES 6 364 #define DRV_SPI_POLLED 1 365 #define DRV_SPI_ISR 0 366 #define DRV_SPI_MASTER 1 367 #define DRV_SPI_SLAVE 0 369 #define DRV_SPI_EBM 1 370 #define DRV_SPI_8BIT 1 371 #define DRV_SPI_16BIT 1 372 #define DRV_SPI_32BIT 0 373 #define DRV_SPI_DMA 0 375 #define DRV_SPI_INSTANCES_NUMBER 3 376 #define DRV_SPI_CLIENTS_NUMBER 3 377 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 379 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 380 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 381 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 382 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 383 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 384 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 385 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 386 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 387 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 388 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 389 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 390 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 391 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 392 #define DRV_SPI_BAUD_RATE_IDX0 1000000 393 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 394 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 395 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 396 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 397 #define DRV_SPI_QUEUE_SIZE_IDX0 10 398 #define DRV_SPI_RESERVED_JOB_IDX0 1 400 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 401 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 402 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 403 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 404 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 405 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 406 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 407 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 408 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 409 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 410 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 411 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 412 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 413 #define DRV_SPI_BAUD_RATE_IDX1 1000000 414 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 415 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 416 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 417 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 418 #define DRV_SPI_QUEUE_SIZE_IDX1 10 419 #define DRV_SPI_RESERVED_JOB_IDX1 1 421 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 422 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 423 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 424 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 425 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 426 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 427 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 428 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 429 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 430 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 431 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 432 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 433 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 434 #define DRV_SPI_BAUD_RATE_IDX2 500000 435 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 436 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 437 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 438 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 439 #define DRV_SPI_QUEUE_SIZE_IDX2 10 440 #define DRV_SPI_RESERVED_JOB_IDX2 1 442 #define DRV_TMR_INTERRUPT_MODE true 444 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 445 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 446 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 447 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 448 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 449 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 450 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 451 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 452 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 453 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 454 #define DRV_TMR_POWER_STATE_IDX0 455 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 456 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 457 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 458 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 459 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 460 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 461 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 462 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 463 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 464 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 465 #define DRV_TMR_POWER_STATE_IDX1 467 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 468 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 469 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 470 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 471 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 472 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 473 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 474 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 475 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 476 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 477 #define DRV_TMR_POWER_STATE_IDX2 479 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 480 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 481 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 482 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 483 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 484 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 485 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 486 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 487 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 488 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 489 #define DRV_TMR_POWER_STATE_IDX3 491 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 492 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 493 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 494 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 495 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 496 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 497 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 498 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 499 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 500 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 501 #define DRV_TMR_POWER_STATE_IDX4 505 #define DRV_USART_INSTANCES_NUMBER 1 506 #define DRV_USART_CLIENTS_NUMBER 1 507 #define DRV_USART_INTERRUPT_MODE false 508 #define DRV_USART_BYTE_MODEL_SUPPORT true 509 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 510 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 518 #define DRV_USBHS_DEVICE_SUPPORT true 520 #define DRV_USBHS_HOST_SUPPORT false 522 #define DRV_USBHS_INSTANCES_NUMBER 1 524 #define DRV_USBHS_INTERRUPT_MODE true 526 #define DRV_USBHS_ENDPOINTS_NUMBER 2 529 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 531 #define USB_DEVICE_INSTANCES_NUMBER 1 533 #define USB_DEVICE_EP0_BUFFER_SIZE 64 535 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 543 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 544 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 545 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 546 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 547 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 549 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 550 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 551 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 552 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 553 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 555 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 556 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 557 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 558 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 559 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 561 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 562 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 563 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 564 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 565 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 567 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 568 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 569 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 570 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 571 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 573 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 574 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 575 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 576 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 577 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 579 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 580 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 581 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 582 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 583 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 585 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 586 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 587 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 588 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 589 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 591 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 592 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 593 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 594 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 595 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 597 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 598 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 599 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 600 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 601 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 603 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 604 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 605 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 606 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 607 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 609 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 610 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 611 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 612 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 613 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 615 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 616 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 617 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 618 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 619 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 621 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 622 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 623 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 624 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 625 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 627 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 628 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 629 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 630 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 631 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 633 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 634 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 635 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 636 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 637 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 639 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 640 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 641 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 642 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 643 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 645 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 646 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 647 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 648 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 649 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 651 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 652 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 653 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 654 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 655 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 657 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 659 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 661 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 663 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 665 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 667 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 669 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 671 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 673 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 675 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 677 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 679 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 681 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 683 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 685 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 687 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 689 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 690 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 691 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 692 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 693 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 694 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 695 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 738 #ifndef _SYS_DEFINITIONS_H 739 #define _SYS_DEFINITIONS_H 748 #include "system/common/sys_common.h" 749 #include "system/common/sys_module.h" 794 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 833 #ifndef _DRV_COMMON_H 834 #define _DRV_COMMON_H 936 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 946 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 956 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1012 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1023 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1038 #define _PLIB_UNSUPPORTED 1046 #include "system/common/sys_module.h" 1058 #define DRV_IC_INDEX_0 0 1059 #define DRV_IC_INDEX_1 1 1060 #define DRV_IC_INDEX_2 2 1061 #define DRV_IC_INDEX_3 3 1062 #define DRV_IC_INDEX_4 4 1063 #define DRV_IC_INDEX_5 5 1064 #define DRV_IC_INDEX_6 6 1065 #define DRV_IC_INDEX_7 7 1066 #define DRV_IC_INDEX_8 8 1067 #define DRV_IC_INDEX_9 9 1068 #define DRV_IC_INDEX_10 10 1069 #define DRV_IC_INDEX_11 11 1070 #define DRV_IC_INDEX_12 12 1071 #define DRV_IC_INDEX_13 13 1072 #define DRV_IC_INDEX_14 14 1073 #define DRV_IC_INDEX_15 15 1105 const SYS_MODULE_INDEX index ,
1106 const SYS_MODULE_INIT *
const init ) ;
1128 const SYS_MODULE_INDEX drvIndex ,
1173 const SYS_MODULE_INDEX drvIndex ,
1306 #ifndef _DRV_IC_STATIC_H 1307 #define _DRV_IC_STATIC_H 1308 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1309 #define DRV_IC_Close( handle ) 1348 #include "system/devcon/sys_devcon.h" 1349 #include "system/clk/sys_clk.h" 1350 #include "system/int/sys_int.h" 1351 #include "system/tmr/sys_tmr.h" 1393 #ifndef _DRV_ADC_STATIC_H 1394 #define _DRV_ADC_STATIC_H 1395 #include <stdbool.h> 1396 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1397 #include "peripheral/adchs/plib_adchs.h" 1398 #include "peripheral/int/plib_int.h" 1438 uint8_t bufIndex ) ;
1442 uint8_t bufIndex ) ;
1492 #ifndef _DRV_TMR_STATIC_H 1493 #define _DRV_TMR_STATIC_H 1542 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1543 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1544 #include "peripheral/tmr/plib_tmr.h" 1580 #ifndef _TMR_DEFINITIONS_PIC32M_H 1581 #define _TMR_DEFINITIONS_PIC32M_H 1639 #include "system/int/sys_int.h" 1640 #include "system/clk/sys_clk.h" 1659 #define DRV_TMR_INDEX_0 0 1660 #define DRV_TMR_INDEX_1 1 1661 #define DRV_TMR_INDEX_2 2 1662 #define DRV_TMR_INDEX_3 3 1663 #define DRV_TMR_INDEX_4 4 1664 #define DRV_TMR_INDEX_5 5 1665 #define DRV_TMR_INDEX_6 6 1666 #define DRV_TMR_INDEX_7 7 1667 #define DRV_TMR_INDEX_8 8 1668 #define DRV_TMR_INDEX_9 9 1669 #define DRV_TMR_INDEX_10 10 1670 #define DRV_TMR_INDEX_11 11 1681 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1766 uint32_t dividerMin ;
1768 uint32_t dividerMax ;
1771 uint32_t dividerStep ;
1787 SYS_MODULE_INIT moduleInit ;
1789 TMR_MODULE_ID tmrId ;
1793 TMR_PRESCALE prescale ;
1797 INT_SOURCE interruptSource ;
1805 bool asyncWriteEnable ;
1820 uint32_t alarmCount ) ;
1882 const SYS_MODULE_INDEX drvIndex ,
1883 const SYS_MODULE_INIT *
const init ) ;
1923 SYS_MODULE_OBJ
object ) ;
1970 SYS_MODULE_OBJ
object ) ;
2004 SYS_MODULE_OBJ
object ) ;
2058 const SYS_MODULE_INDEX index ,
2159 uint32_t counterPeriod ) ;
2649 TMR_PRESCALE preScale ) ;
2889 #ifndef _DRV_TMR_DEPRECATED_H 2890 #define _DRV_TMR_DEPRECATED_H 2931 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 2995 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3060 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3119 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3180 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3239 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3300 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3330 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3362 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3393 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3425 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3487 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3552 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3569 #include "peripheral/tmr/plib_tmr.h" 3570 #include "peripheral/int/plib_int.h" 3572 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3574 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3576 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3578 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3597 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3603 static inline SYS_STATUS
3606 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3617 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3628 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3638 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3647 TMR_PRESCALE prescale ) ;
3678 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3707 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3713 static inline SYS_STATUS
3716 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3727 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3738 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3748 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3757 TMR_PRESCALE prescale ) ;
3788 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3817 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3823 static inline SYS_STATUS
3826 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3837 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3848 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3858 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3867 TMR_PRESCALE prescale ) ;
3898 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3927 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3933 static inline SYS_STATUS
3936 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3947 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3958 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3968 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3977 TMR_PRESCALE prescale ) ;
4008 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4037 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4043 static inline SYS_STATUS
4046 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4057 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4068 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4078 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4087 TMR_PRESCALE prescale ) ;
4118 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4137 #include "peripheral/int/plib_int.h" 4179 #ifndef _DRV_PMP_STATIC_H 4180 #define _DRV_PMP_STATIC_H 4181 #include "peripheral/pmp/plib_pmp.h" 4196 PMP_DATA_WAIT_STATES dataWait ,
4197 PMP_STROBE_WAIT_STATES strobeWait ,
4198 PMP_DATA_HOLD_STATES dataHold ) ;
4253 #ifndef _DRV_USART_STATIC_H 4254 #define _DRV_USART_STATIC_H 4293 #ifndef _DRV_USART_STATIC_LOCAL_H 4294 #define _DRV_USART_STATIC_LOCAL_H 4301 #include <stdbool.h> 4338 #ifndef _DRV_USART_H 4339 #define _DRV_USART_H 4379 #ifndef _DRV_USART_DEFINITIONS_H 4380 #define _DRV_USART_DEFINITIONS_H 4386 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4387 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4424 #ifndef _PLIB_USART_H 4425 #define _PLIB_USART_H 4468 #ifndef _USART_PROCESSOR_H 4469 #define _USART_PROCESSOR_H 4478 #include <stdbool.h> 4479 #error "No Processor Family specified" 4523 USART_MODULE_ID index ) ;
4553 USART_MODULE_ID index ) ;
4585 USART_MODULE_ID index ) ;
4619 USART_MODULE_ID index ,
4620 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4649 USART_BRG_CLOCK_SOURCE
4651 USART_MODULE_ID index ) ;
4705 USART_MODULE_ID index ) ;
4735 USART_MODULE_ID index ) ;
4764 USART_MODULE_ID index ) ;
4796 USART_MODULE_ID index ) ;
4827 USART_MODULE_ID index ) ;
4869 USART_MODULE_ID index ) ;
4902 USART_MODULE_ID index ) ;
4934 USART_MODULE_ID index ) ;
4975 USART_MODULE_ID index ,
4976 uint32_t clockFrequency ,
4977 uint32_t baudRate ) ;
5018 USART_MODULE_ID index ,
5019 uint32_t clockFrequency ,
5020 uint32_t baudRate ) ;
5053 USART_MODULE_ID index ,
5054 int32_t clockFrequency ) ;
5089 USART_MODULE_ID index ,
5124 USART_MODULE_ID index ) ;
5159 USART_MODULE_ID index ,
5194 USART_MODULE_ID index ) ;
5226 USART_MODULE_ID index ) ;
5260 USART_MODULE_ID index ) ;
5293 USART_MODULE_ID index ) ;
5326 USART_MODULE_ID index ) ;
5360 USART_MODULE_ID index ,
5405 USART_MODULE_ID index ) ;
5439 USART_MODULE_ID index ) ;
5475 USART_MODULE_ID index ) ;
5512 USART_MODULE_ID index ,
5552 USART_MODULE_ID index ) ;
5590 USART_MODULE_ID index ) ;
5625 USART_MODULE_ID index ) ;
5659 USART_MODULE_ID index ) ;
5693 USART_MODULE_ID index ) ;
5726 USART_MODULE_ID index ) ;
5758 USART_MODULE_ID index ) ;
5790 USART_MODULE_ID index ) ;
5823 USART_MODULE_ID index ) ;
5857 USART_MODULE_ID index ) ;
5886 USART_MODULE_ID index ) ;
5915 USART_MODULE_ID index ) ;
5947 USART_MODULE_ID index ) ;
5979 USART_MODULE_ID index ) ;
6009 USART_MODULE_ID index ) ;
6039 USART_MODULE_ID index ) ;
6068 USART_MODULE_ID index ) ;
6097 USART_MODULE_ID index ) ;
6131 USART_MODULE_ID index ,
6132 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6164 USART_MODULE_ID index ,
6165 USART_RECEIVE_INTR_MODE interruptMode ) ;
6198 USART_MODULE_ID index ,
6199 USART_LINECONTROL_MODE dataFlowConfig ) ;
6232 USART_MODULE_ID index ,
6233 USART_HANDSHAKE_MODE handshakeConfig ) ;
6266 USART_MODULE_ID index ,
6297 USART_MODULE_ID index ) ;
6326 USART_MODULE_ID index ) ;
6357 USART_MODULE_ID index ) ;
6388 USART_MODULE_ID index ) ;
6418 USART_MODULE_ID index ) ;
6450 USART_MODULE_ID index ,
6451 USART_OPERATION_MODE operationmode ) ;
6481 USART_MODULE_ID index ) ;
6514 USART_MODULE_ID index ) ;
6543 USART_MODULE_ID index ) ;
6573 USART_MODULE_ID index ) ;
6609 USART_MODULE_ID index ) ;
6660 USART_MODULE_ID index ,
6663 bool wakeFromSleep ,
6708 USART_MODULE_ID index ,
6709 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6710 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6711 USART_OPERATION_MODE operationMode ) ;
6757 USART_MODULE_ID index ,
6758 uint32_t systemClock ,
6804 USART_MODULE_ID index ) ;
6825 USART_MODULE_ID index ) ;
6846 USART_MODULE_ID index ) ;
6880 USART_MODULE_ID index ) ;
6907 USART_MODULE_ID index ) ;
6933 USART_MODULE_ID index ) ;
6960 USART_MODULE_ID index ) ;
6986 USART_MODULE_ID index ) ;
7011 USART_MODULE_ID index ) ;
7037 USART_MODULE_ID index ) ;
7062 USART_MODULE_ID index ) ;
7088 USART_MODULE_ID index ) ;
7113 USART_MODULE_ID index ) ;
7139 USART_MODULE_ID index ) ;
7166 USART_MODULE_ID index ) ;
7192 USART_MODULE_ID index ) ;
7218 USART_MODULE_ID index ) ;
7245 USART_MODULE_ID index ) ;
7272 USART_MODULE_ID index ) ;
7299 USART_MODULE_ID index ) ;
7325 USART_MODULE_ID index ) ;
7350 USART_MODULE_ID index ) ;
7376 USART_MODULE_ID index ) ;
7403 USART_MODULE_ID index ) ;
7429 USART_MODULE_ID index ) ;
7455 USART_MODULE_ID index ) ;
7480 USART_MODULE_ID index ) ;
7505 USART_MODULE_ID index ) ;
7530 USART_MODULE_ID index ) ;
7556 USART_MODULE_ID index ) ;
7581 USART_MODULE_ID index ) ;
7607 USART_MODULE_ID index ) ;
7633 USART_MODULE_ID index ) ;
7658 USART_MODULE_ID index ) ;
7684 USART_MODULE_ID index ) ;
7709 USART_MODULE_ID index ) ;
7734 USART_MODULE_ID index ) ;
7761 USART_MODULE_ID index ) ;
7786 USART_MODULE_ID index ) ;
7812 USART_MODULE_ID index ) ;
7877 #include "system/common/sys_common.h" 7878 #include "system/common/sys_module.h" 7890 #include "system/int/sys_int.h" 7962 #ifndef _SYS_DMA_DEFINITIONS_H 7963 #define _SYS_DMA_DEFINITIONS_H 7969 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7970 #include "system/common/sys_common.h" 7971 #include "system/common/sys_module.h" 8041 #ifndef _PLIB_DMA_PROCESSOR_H 8042 #define _PLIB_DMA_PROCESSOR_H 8043 #error "Can't find header" 8087 DMA_MODULE_ID index ,
8088 DMA_CHANNEL channel ) ;
8122 DMA_MODULE_ID index ,
8123 DMA_CHANNEL channel ,
8124 DMA_CHANNEL_COLLISION collisonType ) ;
8156 DMA_MODULE_ID index ,
8157 DMA_CHANNEL channel ) ;
8189 DMA_MODULE_ID index ,
8190 DMA_CHANNEL channel ) ;
8228 DMA_MODULE_ID index ,
8229 DMA_CHANNEL channel ,
8230 DMA_CHANNEL_PRIORITY channelPriority ) ;
8259 DMA_CHANNEL_PRIORITY
8261 DMA_MODULE_ID index ,
8262 DMA_CHANNEL channel ) ;
8290 DMA_MODULE_ID index ,
8291 DMA_CHANNEL_PRIORITY channelPriority ) ;
8316 DMA_CHANNEL_PRIORITY
8318 DMA_MODULE_ID index ) ;
8348 DMA_MODULE_ID index ,
8349 DMA_CHANNEL channel ) ;
8380 DMA_MODULE_ID index ,
8381 DMA_CHANNEL channel ) ;
8410 DMA_MODULE_ID index ,
8411 DMA_CHANNEL channel ) ;
8440 DMA_MODULE_ID index ,
8441 DMA_CHANNEL channel ) ;
8472 DMA_MODULE_ID index ,
8473 DMA_CHANNEL channel ) ;
8502 DMA_MODULE_ID index ,
8503 DMA_CHANNEL channel ) ;
8534 DMA_MODULE_ID index ,
8535 DMA_CHANNEL channel ) ;
8566 DMA_MODULE_ID index ,
8567 DMA_CHANNEL channel ) ;
8596 DMA_MODULE_ID index ,
8597 DMA_CHANNEL channel ) ;
8628 DMA_MODULE_ID index ,
8629 DMA_CHANNEL channel ) ;
8658 DMA_MODULE_ID index ,
8659 DMA_CHANNEL channel ) ;
8689 DMA_MODULE_ID index ,
8690 DMA_CHANNEL channel ) ;
8720 DMA_MODULE_ID index ,
8721 DMA_CHANNEL channel ) ;
8751 DMA_MODULE_ID index ,
8752 DMA_CHANNEL channel ) ;
8782 DMA_MODULE_ID index ,
8783 DMA_CHANNEL channel ) ;
8814 DMA_MODULE_ID index ,
8815 DMA_CHANNEL channel ) ;
8846 DMA_MODULE_ID index ,
8847 DMA_CHANNEL channel ,
8848 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8877 DMA_CHANNEL_TRANSFER_DIRECTION
8879 DMA_MODULE_ID index ,
8880 DMA_CHANNEL channel ) ;
8916 DMA_MODULE_ID index ,
8917 DMA_CHANNEL channel ,
8919 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8952 DMA_MODULE_ID index ,
8953 DMA_CHANNEL channel ,
8954 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8985 DMA_MODULE_ID index ,
8986 DMA_CHANNEL channel ,
8987 uint16_t peripheraladdress ) ;
9015 DMA_MODULE_ID index ,
9016 DMA_CHANNEL channel ) ;
9047 DMA_MODULE_ID index ,
9048 DMA_CHANNEL channel ,
9049 uint16_t transferCount ) ;
9077 DMA_MODULE_ID index ,
9078 DMA_CHANNEL channel ) ;
9111 DMA_MODULE_ID index ,
9112 DMA_CHANNEL channel ,
9113 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9141 DMA_SOURCE_ADDRESSING_MODE
9143 DMA_MODULE_ID index ,
9144 DMA_CHANNEL channel ) ;
9177 DMA_MODULE_ID index ,
9178 DMA_CHANNEL channel ,
9179 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9208 DMA_DESTINATION_ADDRESSING_MODE
9210 DMA_MODULE_ID index ,
9211 DMA_CHANNEL channel ) ;
9244 DMA_MODULE_ID index ,
9245 DMA_CHANNEL channel ,
9246 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9274 DMA_CHANNEL_ADDRESSING_MODE
9276 DMA_MODULE_ID index ,
9277 DMA_CHANNEL channel ) ;
9315 DMA_MODULE_ID index ,
9316 DMA_CHANNEL channel ,
9317 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9353 DMA_MODULE_ID index ,
9354 DMA_CHANNEL channel ,
9355 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9390 DMA_MODULE_ID index ,
9391 DMA_CHANNEL channel ,
9392 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9421 DMA_CHANNEL_INT_SOURCE
9423 DMA_MODULE_ID index ,
9424 DMA_CHANNEL channel ) ;
9459 DMA_MODULE_ID index ,
9460 DMA_CHANNEL channel ,
9461 DMA_TRIGGER_SOURCE IRQnum ) ;
9496 DMA_MODULE_ID index ,
9497 DMA_CHANNEL channel ,
9498 DMA_TRIGGER_SOURCE IRQ ) ;
9529 DMA_MODULE_ID index ,
9530 DMA_CHANNEL channel ,
9531 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9558 DMA_CHANNEL_DATA_SIZE
9560 DMA_MODULE_ID index ,
9561 DMA_CHANNEL channel ) ;
9595 DMA_MODULE_ID index ,
9596 DMA_CHANNEL channel ,
9597 DMA_TRANSFER_MODE channeltransferMode ) ;
9629 DMA_MODULE_ID index ,
9630 DMA_CHANNEL channel ) ;
9659 DMA_MODULE_ID index ,
9660 DMA_CHANNEL channel ) ;
9690 DMA_MODULE_ID index ,
9691 DMA_CHANNEL channel ) ;
9720 DMA_MODULE_ID index ,
9721 DMA_CHANNEL channel ) ;
9749 DMA_MODULE_ID index ,
9750 DMA_CHANNEL channel ) ;
9780 DMA_MODULE_ID index ,
9781 DMA_CHANNEL channel ) ;
9808 DMA_MODULE_ID index ,
9809 DMA_CHANNEL channel ) ;
9845 DMA_MODULE_ID index ,
9846 DMA_CHANNEL channel ) ;
9877 DMA_MODULE_ID index ,
9878 DMA_CHANNEL channel ) ;
9911 DMA_MODULE_ID index ) ;
9940 DMA_MODULE_ID index ) ;
9970 DMA_MODULE_ID index ) ;
9999 DMA_MODULE_ID index ) ;
10028 DMA_MODULE_ID index ) ;
10058 DMA_MODULE_ID index ) ;
10086 DMA_MODULE_ID index ) ;
10114 DMA_MODULE_ID index ) ;
10142 DMA_MODULE_ID index ) ;
10171 DMA_MODULE_ID index ) ;
10199 DMA_MODULE_ID index ) ;
10233 DMA_MODULE_ID index ) ;
10263 DMA_MODULE_ID index ) ;
10293 DMA_MODULE_ID index ) ;
10322 DMA_MODULE_ID index ) ;
10357 DMA_MODULE_ID index ,
10358 DMA_CHANNEL channel ) ;
10387 DMA_MODULE_ID index ) ;
10419 DMA_MODULE_ID index ,
10420 DMA_CRC_TYPE CRCType ) ;
10451 DMA_MODULE_ID index ) ;
10481 DMA_MODULE_ID index ) ;
10511 DMA_MODULE_ID index ) ;
10541 DMA_MODULE_ID index ) ;
10570 DMA_MODULE_ID index ) ;
10600 DMA_MODULE_ID index ) ;
10629 DMA_MODULE_ID index ) ;
10659 DMA_MODULE_ID index ,
10660 uint8_t polyLength ) ;
10689 DMA_MODULE_ID index ) ;
10718 DMA_MODULE_ID index ,
10719 DMA_CRC_BIT_ORDER bitOrder ) ;
10750 DMA_MODULE_ID index ) ;
10779 DMA_MODULE_ID index ) ;
10809 DMA_MODULE_ID index ,
10810 DMA_CRC_BYTE_ORDER byteOrder ) ;
10839 DMA_MODULE_ID index ) ;
10870 DMA_MODULE_ID index ) ;
10902 DMA_MODULE_ID index ,
10903 uint32_t DMACRCdata ) ;
10934 DMA_MODULE_ID index ) ;
10967 DMA_MODULE_ID index ,
10968 uint32_t DMACRCXOREnableMask ) ;
11006 DMA_MODULE_ID index ,
11007 DMA_CHANNEL dmaChannel ) ;
11044 DMA_MODULE_ID index ,
11045 DMA_CHANNEL dmaChannel ,
11046 uint32_t sourceStartAddress ) ;
11080 DMA_MODULE_ID index ,
11081 DMA_CHANNEL dmaChannel ) ;
11119 DMA_MODULE_ID index ,
11120 DMA_CHANNEL dmaChannel ,
11121 uint32_t destinationStartAddress ) ;
11161 DMA_MODULE_ID index ,
11162 DMA_CHANNEL dmaChannel ) ;
11201 DMA_MODULE_ID index ,
11202 DMA_CHANNEL dmaChannel ,
11203 uint16_t sourceSize ) ;
11238 DMA_MODULE_ID index ,
11239 DMA_CHANNEL dmaChannel ) ;
11276 DMA_MODULE_ID index ,
11277 DMA_CHANNEL dmaChannel ,
11278 uint16_t destinationSize ) ;
11312 DMA_MODULE_ID index ,
11313 DMA_CHANNEL dmaChannel ) ;
11348 DMA_MODULE_ID index ,
11349 DMA_CHANNEL dmaChannel ) ;
11384 DMA_MODULE_ID index ,
11385 DMA_CHANNEL dmaChannel ) ;
11422 DMA_MODULE_ID index ,
11423 DMA_CHANNEL dmaChannel ,
11424 uint16_t CellSize ) ;
11458 DMA_MODULE_ID index ,
11459 DMA_CHANNEL dmaChannel ) ;
11496 DMA_MODULE_ID index ,
11497 DMA_CHANNEL dmaChannel ) ;
11536 DMA_MODULE_ID index ,
11537 DMA_CHANNEL dmaChannel ,
11538 uint16_t patternData ) ;
11582 DMA_MODULE_ID index ,
11583 DMA_CHANNEL dmaChannel ,
11584 DMA_INT_TYPE dmaINTSource ) ;
11619 DMA_MODULE_ID index ,
11620 DMA_CHANNEL dmaChannel ,
11621 DMA_INT_TYPE dmaINTSource ) ;
11657 DMA_MODULE_ID index ,
11658 DMA_CHANNEL dmaChannel ,
11659 DMA_INT_TYPE dmaINTSource ) ;
11693 DMA_MODULE_ID index ,
11694 DMA_CHANNEL dmaChannel ,
11695 DMA_INT_TYPE dmaINTSource ) ;
11729 DMA_MODULE_ID index ,
11730 DMA_CHANNEL dmaChannel ,
11731 DMA_INT_TYPE dmaINTSource ) ;
11769 DMA_MODULE_ID index ,
11770 DMA_CHANNEL dmaChannel ,
11771 DMA_INT_TYPE dmaINTSource ) ;
11804 DMA_MODULE_ID index ,
11805 DMA_CHANNEL dmaChannel ,
11806 DMA_PATTERN_LENGTH patternLen ) ;
11839 DMA_MODULE_ID index ,
11840 DMA_CHANNEL dmaChannel ) ;
11870 DMA_MODULE_ID index ,
11871 DMA_CHANNEL channel ) ;
11904 DMA_MODULE_ID index ,
11905 DMA_CHANNEL channel ) ;
11935 DMA_MODULE_ID index ,
11936 DMA_CHANNEL channel ) ;
11968 DMA_MODULE_ID index ,
11969 DMA_CHANNEL channel ,
11970 uint8_t pattern ) ;
12001 DMA_MODULE_ID index ,
12002 DMA_CHANNEL channel ) ;
12034 DMA_MODULE_ID index ) ;
12059 DMA_MODULE_ID index ) ;
12083 DMA_MODULE_ID index ) ;
12108 DMA_MODULE_ID index ) ;
12131 DMA_MODULE_ID index ) ;
12155 DMA_MODULE_ID index ) ;
12178 DMA_MODULE_ID index ) ;
12202 DMA_MODULE_ID index ) ;
12226 DMA_MODULE_ID index ) ;
12251 DMA_MODULE_ID index ) ;
12275 DMA_MODULE_ID index ) ;
12299 DMA_MODULE_ID index ) ;
12322 DMA_MODULE_ID index ) ;
12346 DMA_MODULE_ID index ) ;
12370 DMA_MODULE_ID index ) ;
12394 DMA_MODULE_ID index ) ;
12418 DMA_MODULE_ID index ) ;
12442 DMA_MODULE_ID index ) ;
12465 DMA_MODULE_ID index ) ;
12490 DMA_MODULE_ID index ) ;
12515 DMA_MODULE_ID index ) ;
12539 DMA_MODULE_ID index ) ;
12564 DMA_MODULE_ID index ) ;
12588 DMA_MODULE_ID index ) ;
12612 DMA_MODULE_ID index ) ;
12638 DMA_MODULE_ID index ) ;
12663 DMA_MODULE_ID index ) ;
12687 DMA_MODULE_ID index ) ;
12712 DMA_MODULE_ID index ) ;
12735 DMA_MODULE_ID index ) ;
12758 DMA_MODULE_ID index ) ;
12781 DMA_MODULE_ID index ) ;
12804 DMA_MODULE_ID index ) ;
12829 DMA_MODULE_ID index ) ;
12854 DMA_MODULE_ID index ) ;
12878 DMA_MODULE_ID index ) ;
12903 DMA_MODULE_ID index ) ;
12927 DMA_MODULE_ID index ) ;
12951 DMA_MODULE_ID index ) ;
12974 DMA_MODULE_ID index ) ;
12997 DMA_MODULE_ID index ) ;
13021 DMA_MODULE_ID index ) ;
13045 DMA_MODULE_ID index ) ;
13069 DMA_MODULE_ID index ) ;
13096 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13109 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13122 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13152 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13326 DMA_CRC_TYPE type ;
13332 uint8_t polyLength ;
13335 DMA_CRC_BIT_ORDER bitOrder ;
13338 DMA_CRC_BYTE_ORDER byteOrder ;
13348 uint32_t xorBitMask ;
13473 SYS_MODULE_OBJ
object ,
13474 DMA_CHANNEL activeChannel ) ;
13477 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13522 uintptr_t contextHandle ) ;
13568 const SYS_MODULE_INIT *
const init ) ;
13619 DMA_CHANNEL channel ) ;
13705 DMA_TRIGGER_SOURCE eventSrc ) ;
13783 DMA_PATTERN_LENGTH length ,
13785 uint8_t ignorePattern ) ;
14038 const void * srcAddr ,
14040 const void * destAddr ,
14042 size_t cellSize ) ;
14139 const void * srcAddr ,
14141 const void * destAddr ,
14143 size_t cellSize ) ;
14339 const uintptr_t contextHandle ) ;
14635 DMA_TRIGGER_SOURCE eventSrc ) ;
14814 SYS_MODULE_OBJ
object ,
14815 DMA_CHANNEL activeChannel ) ;
14825 SYS_MODULE_OBJ
object ) ;
14835 SYS_MODULE_OBJ
object ,
14836 DMA_CHANNEL activeChannel ) ;
14863 #define DRV_USART_INDEX_0 0 14864 #define DRV_USART_INDEX_1 1 14865 #define DRV_USART_INDEX_2 2 14866 #define DRV_USART_INDEX_3 3 14867 #define DRV_USART_INDEX_4 4 14868 #define DRV_USART_INDEX_5 5 14882 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14893 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14904 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14938 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15089 uintptr_t context ) ;
15137 USART_HANDSHAKE_MODE_FLOW_CONTROL
15141 USART_HANDSHAKE_MODE_SIMPLEX
15303 } AddressedModeInit ;
15328 = USART_ERROR_PARITY
15333 = USART_ERROR_FRAMING
15338 = USART_ERROR_RECEIVER_OVERRUN
15420 SYS_MODULE_INIT moduleInit ;
15424 USART_MODULE_ID usartID ;
15442 uint32_t brgClock ;
15458 USART_OPERATION_MODE linesEnable ;
15462 INT_SOURCE interruptTransmit ;
15466 INT_SOURCE interruptReceive ;
15470 INT_SOURCE interruptError ;
15475 unsigned int queueSizeReceive ;
15480 unsigned int queueSizeTransmit ;
15484 DMA_CHANNEL dmaChannelTransmit ;
15488 DMA_CHANNEL dmaChannelReceive ;
15492 INT_SOURCE dmaInterruptTransmit ;
15496 INT_SOURCE dmaInterruptReceive ;
15580 const SYS_MODULE_INDEX index ,
15581 const SYS_MODULE_INIT *
const init ) ;
15619 SYS_MODULE_OBJ
object ) ;
15657 SYS_MODULE_OBJ
object ) ;
15698 SYS_MODULE_OBJ
object ) ;
15739 SYS_MODULE_OBJ
object ) ;
15780 SYS_MODULE_OBJ
object ) ;
15859 const SYS_MODULE_INDEX index ,
16043 const size_t size ) ;
16236 const size_t size ) ;
16324 const uintptr_t context ) ;
16591 const size_t numbytes ) ;
16659 const size_t numbytes ) ;
16796 const uint8_t byte ) ;
17014 const SYS_MODULE_INDEX index ,
17067 const SYS_MODULE_INDEX index ,
17116 const SYS_MODULE_INDEX index ,
17331 #ifndef _DRV_USART_FEATURE_MAPPING_H 17332 #define _DRV_USART_FEATURE_MAPPING_H 17341 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17342 #define _DRV_USART_InterruptSourceEnable( source ) 17343 #define _DRV_USART_InterruptSourceDisable( source ) false 17344 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17345 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17346 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17347 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17348 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17351 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17360 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17361 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17362 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17363 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17364 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17377 #include "system/clk/sys_clk.h" 17378 #include "system/int/sys_int.h" 17416 #ifndef _SYS_DEBUG_H 17417 #define _SYS_DEBUG_H 17418 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17421 #define SYS_DEBUG_BUFFER_DMA_READY 17471 #define SYS_DEBUG_INDEX_0 0 17487 SYS_MODULE_INIT moduleInit ;
17491 SYS_MODULE_INDEX consoleIndex ;
17539 const SYS_MODULE_INDEX index ,
17540 const SYS_MODULE_INIT *
const init ) ;
17580 SYS_MODULE_OBJ
object ,
17581 const SYS_MODULE_INIT *
const init ) ;
17611 SYS_MODULE_OBJ
object ) ;
17644 SYS_MODULE_OBJ
object ) ;
17688 SYS_MODULE_OBJ
object ) ;
17731 const char * message ) ;
17781 const char * format ,
17871 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17915 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17958 #define SYS_MESSAGE( message ) 17991 #define SYS_DEBUG_MESSAGE( level , message ) 18038 #define SYS_PRINT( fmt ,... ) 18086 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18111 #define SYS_DEBUG_BreakPoint( ) 18120 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18121 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18122 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18139 #define _DRV_USART_RX_DEPTH 9 18205 const SYS_MODULE_INDEX index ,
18230 const uint8_t byte ) ;
18301 #ifndef _SYS_PORTS_H 18302 #define _SYS_PORTS_H 18341 #ifndef _SYS_PORTS_DEFINITIONS_H 18342 #define _SYS_PORTS_DEFINITIONS_H 18348 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18349 #include "system/common/sys_common.h" 18350 #include "system/common/sys_module.h" 18387 #ifndef _PLIB_PORTS_H 18388 #define _PLIB_PORTS_H 18389 #include <stdint.h> 18390 #include <stddef.h> 18455 #ifndef _PLIB_PORTS_PROCESSOR_H 18456 #define _PLIB_PORTS_PROCESSOR_H 18457 #error "Can't find header" 18507 PORTS_MODULE_ID index ,
18508 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18509 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18552 PORTS_MODULE_ID index ,
18553 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18554 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18589 PORTS_MODULE_ID index ,
18590 PORTS_ANALOG_PIN pin ,
18591 PORTS_PIN_MODE mode ) ;
18631 PORTS_MODULE_ID index ,
18632 PORTS_CHANNEL channel ,
18633 PORTS_BIT_POS bitPos ,
18634 PORTS_PIN_MODE mode ) ;
18669 PORTS_MODULE_ID index ,
18670 PORTS_CHANNEL channel ,
18671 PORTS_BIT_POS bitPos ) ;
18705 PORTS_MODULE_ID index ,
18706 PORTS_CHANNEL channel ,
18707 PORTS_BIT_POS bitPos ) ;
18744 PORTS_MODULE_ID index ,
18745 PORTS_CHANNEL channel ,
18746 PORTS_BIT_POS bitPos ) ;
18787 PORTS_MODULE_ID index ,
18788 PORTS_CHANNEL channel ,
18789 PORTS_BIT_POS bitPos ) ;
18828 PORTS_MODULE_ID index ,
18829 PORTS_CHANNEL channel ,
18830 PORTS_BIT_POS bitPos ) ;
18868 PORTS_MODULE_ID index ,
18869 PORTS_CHANNEL channel ,
18870 PORTS_BIT_POS bitPos ) ;
18905 PORTS_MODULE_ID index ,
18906 PORTS_CHANNEL channel ) ;
18941 PORTS_MODULE_ID index ,
18942 PORTS_CHANNEL channel ) ;
18979 PORTS_MODULE_ID index ,
18980 PORTS_CHANNEL channel ) ;
19017 PORTS_MODULE_ID index ,
19018 PORTS_CHANNEL channel ) ;
19055 PORTS_MODULE_ID index ,
19056 PORTS_CHANNEL channel ,
19057 PORTS_BIT_POS bitPos ) ;
19094 PORTS_MODULE_ID index ,
19095 PORTS_CHANNEL channel ,
19096 PORTS_BIT_POS bitPos ) ;
19134 PORTS_MODULE_ID index ,
19135 PORTS_CHANNEL channel ,
19136 PORTS_BIT_POS bitPos ) ;
19173 PORTS_MODULE_ID index ,
19174 PORTS_CHANNEL channel ,
19175 PORTS_BIT_POS bitPos ,
19210 PORTS_MODULE_ID index ,
19211 PORTS_CHANNEL channel ,
19212 PORTS_BIT_POS bitPos ) ;
19246 PORTS_MODULE_ID index ,
19247 PORTS_CHANNEL channel ,
19248 PORTS_BIT_POS bitPos ) ;
19282 PORTS_MODULE_ID index ,
19283 PORTS_CHANNEL channel ,
19284 PORTS_BIT_POS bitPos ) ;
19319 PORTS_MODULE_ID index ,
19320 PORTS_CHANNEL channel ,
19321 PORTS_BIT_POS bitPos ) ;
19356 PORTS_MODULE_ID index ,
19357 PORTS_CHANNEL channel ,
19358 PORTS_BIT_POS bitPos ) ;
19392 PORTS_MODULE_ID index ,
19393 PORTS_CHANNEL channel ,
19394 PORTS_BIT_POS bitPos ) ;
19428 PORTS_MODULE_ID index ,
19429 PORTS_CHANNEL channel ,
19430 PORTS_BIT_POS bitPos ) ;
19468 PORTS_MODULE_ID index ,
19469 PORTS_CHANNEL channel ) ;
19503 PORTS_MODULE_ID index ,
19504 PORTS_CHANNEL channel ) ;
19538 PORTS_MODULE_ID index ,
19539 PORTS_CHANNEL channel ,
19582 PORTS_MODULE_ID index ,
19583 PORTS_CHANNEL channel ,
19619 PORTS_MODULE_ID index ,
19620 PORTS_CHANNEL channel ,
19655 PORTS_MODULE_ID index ,
19656 PORTS_CHANNEL channel ,
19692 PORTS_MODULE_ID index ,
19693 PORTS_CHANNEL channel ,
19728 PORTS_MODULE_ID index ,
19729 PORTS_CHANNEL channel ,
19762 PORTS_MODULE_ID index ,
19763 PORTS_CHANNEL channel ) ;
19797 PORTS_MODULE_ID index ,
19798 PORTS_CHANNEL channel ,
19834 PORTS_MODULE_ID index ,
19835 PORTS_CHANNEL channel ,
19881 PORTS_MODULE_ID index ,
19882 PORTS_CHANNEL channel ,
19884 PORTS_PIN_MODE mode ) ;
19926 PORTS_MODULE_ID index ,
19927 PORTS_CHANNEL channel ,
19970 PORTS_MODULE_ID index ,
19971 PORTS_CHANNEL channel ,
20011 PORTS_MODULE_ID index ,
20012 PORTS_CHANNEL channel ,
20052 PORTS_MODULE_ID index ,
20053 PORTS_CHANNEL channel ,
20097 PORTS_MODULE_ID index ,
20098 PORTS_CHANNEL channel ,
20142 PORTS_MODULE_ID index ,
20143 PORTS_CHANNEL channel ,
20189 PORTS_MODULE_ID index ,
20190 PORTS_AN_PIN anPins ,
20191 PORTS_PIN_MODE mode ) ;
20234 PORTS_MODULE_ID index ,
20235 PORTS_CN_PIN cnPins ) ;
20279 PORTS_MODULE_ID index ,
20280 PORTS_CN_PIN cnPins ) ;
20323 PORTS_MODULE_ID index ,
20324 PORTS_CN_PIN cnPins ) ;
20367 PORTS_MODULE_ID index ,
20368 PORTS_CN_PIN cnPins ) ;
20402 PORTS_MODULE_ID index ) ;
20435 PORTS_MODULE_ID index ) ;
20471 PORTS_MODULE_ID index ,
20472 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20508 PORTS_MODULE_ID index ,
20509 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20546 PORTS_MODULE_ID index ) ;
20580 PORTS_MODULE_ID index ) ;
20616 PORTS_MODULE_ID index ,
20617 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20653 PORTS_MODULE_ID index ,
20654 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20699 PORTS_MODULE_ID index ,
20700 PORTS_CHANNEL channel ,
20702 PORTS_PIN_SLEW_RATE slewRate ) ;
20739 PORTS_PIN_SLEW_RATE
20741 PORTS_MODULE_ID index ,
20742 PORTS_CHANNEL channel ,
20743 PORTS_BIT_POS bitPos ) ;
20782 PORTS_MODULE_ID index ,
20783 PORTS_CHANNEL channel ,
20784 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20817 PORTS_CHANGE_NOTICE_METHOD
20819 PORTS_MODULE_ID index ,
20820 PORTS_CHANNEL channel ) ;
20868 PORTS_MODULE_ID index ,
20869 PORTS_CHANNEL channel ,
20919 PORTS_MODULE_ID index ,
20920 PORTS_CHANNEL channel ,
20968 PORTS_MODULE_ID index ,
20969 PORTS_CHANNEL channel ,
20970 PORTS_BIT_POS bitPos ,
20971 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21014 PORTS_MODULE_ID index ,
21015 PORTS_CHANNEL channel ,
21016 PORTS_BIT_POS bitPos ) ;
21047 PORTS_MODULE_ID index ) ;
21071 PORTS_MODULE_ID index ) ;
21095 PORTS_MODULE_ID index ) ;
21119 PORTS_MODULE_ID index ) ;
21144 PORTS_MODULE_ID index ) ;
21169 PORTS_MODULE_ID index ) ;
21200 PORTS_MODULE_ID index ) ;
21228 PORTS_MODULE_ID index ) ;
21255 PORTS_MODULE_ID index ) ;
21280 PORTS_MODULE_ID index ) ;
21307 PORTS_MODULE_ID index ) ;
21332 PORTS_MODULE_ID index ) ;
21359 PORTS_MODULE_ID index ) ;
21384 PORTS_MODULE_ID index ) ;
21412 PORTS_MODULE_ID index ) ;
21440 PORTS_MODULE_ID index ) ;
21468 PORTS_MODULE_ID index ) ;
21494 PORTS_MODULE_ID index ) ;
21520 PORTS_MODULE_ID index ) ;
21546 PORTS_MODULE_ID index ) ;
21571 PORTS_MODULE_ID index ) ;
21597 PORTS_MODULE_ID index ) ;
21624 PORTS_MODULE_ID index ) ;
21649 PORTS_MODULE_ID index ) ;
21684 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21685 #define _PLIB_PORTS_COMPATIBILITY_H 21686 #include <stdint.h> 21687 #include <stddef.h> 21722 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21739 #include "system/int/sys_int.h" 21873 PORTS_MODULE_ID index ,
21874 PORTS_CHANNEL channel ) ;
21906 PORTS_MODULE_ID index ,
21907 PORTS_CHANNEL channel ,
21937 PORTS_MODULE_ID index ,
21938 PORTS_CHANNEL channel ) ;
21976 PORTS_MODULE_ID index ,
21977 PORTS_CHANNEL channel ,
22011 PORTS_MODULE_ID index ,
22012 PORTS_CHANNEL channel ,
22049 PORTS_MODULE_ID index ,
22051 PORTS_CHANNEL channel ,
22081 PORTS_MODULE_ID index ,
22082 PORTS_CHANNEL channel ) ;
22113 PORTS_MODULE_ID index ,
22114 PORTS_CHANNEL channel ,
22146 PORTS_MODULE_ID index ,
22147 PORTS_CHANNEL channel ,
22179 PORTS_MODULE_ID index ,
22180 PORTS_CHANNEL channel ,
22214 PORTS_MODULE_ID index ,
22215 PORTS_CHANNEL channel ) ;
22255 PORTS_MODULE_ID index ,
22256 PORTS_REMAP_INPUT_FUNCTION
function ,
22257 PORTS_REMAP_INPUT_PIN remapPin ) ;
22292 PORTS_MODULE_ID index ,
22293 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22294 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22327 PORTS_MODULE_ID index ) ;
22355 PORTS_MODULE_ID index ) ;
22389 PORTS_MODULE_ID index ,
22390 PORTS_CHANGE_NOTICE_PIN pinNum ,
22422 PORTS_MODULE_ID index ,
22423 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22452 PORTS_MODULE_ID index ) ;
22481 PORTS_MODULE_ID index ) ;
22512 PORTS_MODULE_ID index ,
22513 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22544 PORTS_MODULE_ID index ,
22545 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22584 PORTS_MODULE_ID index ,
22585 PORTS_ANALOG_PIN pin ,
22586 PORTS_PIN_MODE mode ) ;
22623 PORTS_MODULE_ID index ,
22624 PORTS_CHANNEL channel ,
22625 PORTS_BIT_POS bitPos ,
22660 PORTS_MODULE_ID index ,
22661 PORTS_CHANNEL channel ,
22662 PORTS_BIT_POS bitPos ) ;
22695 PORTS_MODULE_ID index ,
22696 PORTS_CHANNEL channel ,
22697 PORTS_BIT_POS bitPos ) ;
22730 PORTS_MODULE_ID index ,
22731 PORTS_CHANNEL channel ,
22732 PORTS_BIT_POS bitPos ) ;
22765 PORTS_MODULE_ID index ,
22766 PORTS_CHANNEL channel ,
22767 PORTS_BIT_POS bitPos ) ;
22800 PORTS_MODULE_ID index ,
22801 PORTS_CHANNEL channel ,
22802 PORTS_BIT_POS bitPos ) ;
22839 PORTS_MODULE_ID index ,
22841 PORTS_CHANNEL channel ,
22842 PORTS_BIT_POS bitPos ) ;
22875 PORTS_MODULE_ID index ,
22876 PORTS_CHANNEL channel ,
22877 PORTS_BIT_POS bitPos ) ;
22910 PORTS_MODULE_ID index ,
22911 PORTS_CHANNEL channel ,
22912 PORTS_BIT_POS bitPos ) ;
22945 PORTS_MODULE_ID index ,
22946 PORTS_CHANNEL channel ,
22947 PORTS_BIT_POS bitPos ) ;
22980 PORTS_MODULE_ID index ,
22981 PORTS_CHANNEL channel ,
22982 PORTS_BIT_POS bitPos ) ;
23015 PORTS_MODULE_ID index ,
23016 PORTS_CHANNEL channel ,
23017 PORTS_BIT_POS bitPos ) ;
23050 PORTS_MODULE_ID index ,
23051 PORTS_CHANNEL channel ,
23052 PORTS_BIT_POS bitPos ) ;
23085 PORTS_MODULE_ID index ,
23086 PORTS_CHANNEL channel ,
23087 PORTS_BIT_POS bitPos ,
23170 #ifndef _DRV_SPI_DEFINITIONS_H 23171 #define _DRV_SPI_DEFINITIONS_H 23177 #include <stdint.h> 23178 #include <stdbool.h> 23179 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23180 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23216 #ifndef _PLIB_SPI_H 23217 #define _PLIB_SPI_H 23251 #ifndef _PLIB_SPI_PROCESSOR_H 23252 #define _PLIB_SPI_PROCESSOR_H 23253 #error "Can't find header" 23298 SPI_MODULE_ID index ) ;
23328 SPI_MODULE_ID index ) ;
23360 SPI_MODULE_ID index ) ;
23392 SPI_MODULE_ID index ) ;
23426 SPI_MODULE_ID index ) ;
23456 SPI_MODULE_ID index ) ;
23493 SPI_MODULE_ID index ) ;
23532 SPI_MODULE_ID index ) ;
23562 SPI_MODULE_ID index ,
23593 SPI_MODULE_ID index ,
23627 SPI_MODULE_ID index ,
23628 SPI_COMMUNICATION_WIDTH width ) ;
23663 SPI_MODULE_ID index ,
23664 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23696 SPI_MODULE_ID index ,
23697 SPI_INPUT_SAMPLING_PHASE phase ) ;
23729 SPI_MODULE_ID index ,
23730 SPI_OUTPUT_DATA_PHASE phase ) ;
23761 SPI_MODULE_ID index ,
23762 SPI_CLOCK_POLARITY polarity ) ;
23792 SPI_MODULE_ID index ) ;
23822 SPI_MODULE_ID index ) ;
23860 SPI_MODULE_ID index ,
23861 uint32_t clockFrequency ,
23862 uint32_t baudRate ) ;
23893 SPI_MODULE_ID index ) ;
23925 SPI_MODULE_ID index ) ;
23958 SPI_MODULE_ID index ) ;
23991 SPI_MODULE_ID index ) ;
24023 SPI_MODULE_ID index ) ;
24053 SPI_MODULE_ID index ) ;
24084 SPI_MODULE_ID index ) ;
24115 SPI_MODULE_ID index ) ;
24146 SPI_MODULE_ID index ) ;
24178 SPI_MODULE_ID index ,
24179 SPI_FIFO_TYPE type ) ;
24211 SPI_MODULE_ID index ) ;
24243 SPI_MODULE_ID index ) ;
24277 SPI_MODULE_ID index ,
24278 SPI_FIFO_INTERRUPT mode ) ;
24308 SPI_MODULE_ID index ) ;
24338 SPI_MODULE_ID index ) ;
24370 SPI_MODULE_ID index ,
24371 SPI_FRAME_PULSE_DIRECTION direction ) ;
24404 SPI_MODULE_ID index ,
24405 SPI_FRAME_PULSE_POLARITY polarity ) ;
24438 SPI_MODULE_ID index ,
24439 SPI_FRAME_PULSE_EDGE edge ) ;
24472 SPI_MODULE_ID index ,
24473 SPI_FRAME_PULSE_WIDTH width ) ;
24507 SPI_MODULE_ID index ,
24508 SPI_FRAME_SYNC_PULSE pulse ) ;
24540 SPI_MODULE_ID index ) ;
24570 SPI_MODULE_ID index ) ;
24602 SPI_MODULE_ID index ) ;
24632 SPI_MODULE_ID index ) ;
24662 SPI_MODULE_ID index ) ;
24692 SPI_MODULE_ID index ) ;
24723 SPI_MODULE_ID index ,
24755 SPI_MODULE_ID index ,
24787 SPI_MODULE_ID index ,
24810 SPI_MODULE_ID index ) ;
24841 SPI_MODULE_ID index ,
24842 SPI_BAUD_RATE_CLOCK type ) ;
24874 SPI_MODULE_ID index ,
24875 SPI_ERROR_INTERRUPT error ) ;
24907 SPI_MODULE_ID index ,
24908 SPI_ERROR_INTERRUPT error ) ;
24939 SPI_MODULE_ID index ,
24940 SPI_AUDIO_ERROR error ) ;
24971 SPI_MODULE_ID index ,
24972 SPI_AUDIO_ERROR error ) ;
25002 SPI_MODULE_ID index ) ;
25032 SPI_MODULE_ID index ) ;
25064 SPI_MODULE_ID index ,
25065 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25097 SPI_MODULE_ID index ,
25098 SPI_AUDIO_PROTOCOL mode ) ;
25131 SPI_MODULE_ID index ) ;
25157 SPI_MODULE_ID index ) ;
25183 SPI_MODULE_ID index ) ;
25208 SPI_MODULE_ID index ) ;
25233 SPI_MODULE_ID index ) ;
25258 SPI_MODULE_ID index ) ;
25284 SPI_MODULE_ID index ) ;
25309 SPI_MODULE_ID index ) ;
25334 SPI_MODULE_ID index ) ;
25359 SPI_MODULE_ID index ) ;
25384 SPI_MODULE_ID index ) ;
25409 SPI_MODULE_ID index ) ;
25435 SPI_MODULE_ID index ) ;
25460 SPI_MODULE_ID index ) ;
25485 SPI_MODULE_ID index ) ;
25510 SPI_MODULE_ID index ) ;
25536 SPI_MODULE_ID index ) ;
25562 SPI_MODULE_ID index ) ;
25588 SPI_MODULE_ID index ) ;
25612 SPI_MODULE_ID index ) ;
25637 SPI_MODULE_ID index ) ;
25662 SPI_MODULE_ID index ) ;
25687 SPI_MODULE_ID index ) ;
25713 SPI_MODULE_ID index ) ;
25738 SPI_MODULE_ID index ) ;
25763 SPI_MODULE_ID index ) ;
25788 SPI_MODULE_ID index ) ;
25813 SPI_MODULE_ID index ) ;
25838 SPI_MODULE_ID index ) ;
25864 SPI_MODULE_ID index ) ;
25891 SPI_MODULE_ID index ) ;
25916 SPI_MODULE_ID index ) ;
25942 SPI_MODULE_ID index ) ;
25968 SPI_MODULE_ID index ) ;
25994 SPI_MODULE_ID index ) ;
26019 SPI_MODULE_ID index ) ;
26044 SPI_MODULE_ID index ) ;
26070 SPI_MODULE_ID index ) ;
26096 SPI_MODULE_ID index ) ;
26108 #include "system/common/sys_common.h" 26109 #include "system/common/sys_module.h" 26110 #include "system/int/sys_int.h" 26111 #include "system/clk/sys_clk.h" 26112 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26150 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26162 #define DRV_SPI_INDEX_0 0 26163 #define DRV_SPI_INDEX_1 1 26164 #define DRV_SPI_INDEX_2 2 26165 #define DRV_SPI_INDEX_3 3 26166 #define DRV_SPI_INDEX_4 4 26167 #define DRV_SPI_INDEX_5 5 26179 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26428 SPI_MODULE_ID
spiId ;
26461 CLK_BUSES_PERIPHERAL
spiClk ;
26621 const SYS_MODULE_INDEX index ,
26622 const SYS_MODULE_INIT *
const init ) ;
26664 SYS_MODULE_OBJ
object ) ;
26713 SYS_MODULE_OBJ
object ) ;
26754 SYS_MODULE_OBJ
object ) ;
26819 const SYS_MODULE_INDEX drvIndex ,
27443 #include <stdint.h> 27463 uint8_t RevNumber ;
27550 SYS_MODULE_OBJ sysTmr ;
27551 SYS_MODULE_OBJ drvTmr0 ;
27552 SYS_MODULE_OBJ drvTmr1 ;
27553 SYS_MODULE_OBJ drvTmr2 ;
27554 SYS_MODULE_OBJ drvTmr3 ;
27555 SYS_MODULE_OBJ drvTmr4 ;
27556 SYS_MODULE_OBJ drvUsart0 ;
27557 SYS_MODULE_OBJ drvPMP0 ;
27559 SYS_MODULE_OBJ spiObjectIdx0 ;
27561 SYS_MODULE_OBJ spiObjectIdx1 ;
27563 SYS_MODULE_OBJ spiObjectIdx2 ;
27564 SYS_MODULE_OBJ drvUSBObject ;
27565 SYS_MODULE_OBJ usbDevObject0 ;
27611 #include <stdint.h> 27612 #include <stdbool.h> 27618 #define S3_NUM_OF_POSITIONS 5U 27619 #define S6_NUM_OF_POSITIONS 3U 27620 #define S4_NUM_OF_POSITIONS 2U 27621 #define S1_NUM_OF_POSITIONS 2U 27661 uint8_t knob_switch_S3 [ 5 ] ;
27662 uint8_t key_switch_S6 [ 3 ] ;
27663 uint8_t pol_switch_S4 [ 2 ] ;
27665 uint8_t fire_switch_S1 [ 2 ] ;
27671 uint16_t store_buffer [ 2 ] ;
27955 #include <stdint.h> 27956 #include <stdbool.h> 27996 uint16_t hvps_cont ;
27997 uint16_t wl_cps_i ;
27998 uint16_t wl_cps_v ;
27999 uint16_t wl_sps_i_cf ;
28000 uint16_t wl_sps_i ;
28064 #ifndef COMMMODULE_H 28065 #define COMMMODULE_H 28071 #include "../system_definitions.h" 28212 #include "../system_definitions.h" 28262 bool spi_write_complete_flag ;
28263 bool spi_sent_flag ;
28264 uint16_t adj [ 1 ] ;
28267 bool new_cont_values_flag ;
28269 uint16_t cont_prev ;
28270 uint16_t cont_new ;
28274 uint16_t update_rate ;
28276 uint16_t update_count ;
28280 uint16_t sensor_offset ;
28282 uint16_t sensor_constant ;
28283 uint16_t max_current ;
28284 uint16_t current_limit ;
28285 uint16_t upper_current_limit ;
28286 uint8_t over_current_count ;
28287 bool new_current_values_flag ;
28288 bool new_voltage_values_flag ;
28289 bool overcurrent_flag ;
28290 bool overvoltage_flag ;
28391 #include "../system_config.h" 28392 #include "../system_definitions.h" 28393 #include <stdbool.h> 28402 #define NEGATIVE_OFFSET 0x02U 28403 #define POS_HIGH_OFFSET 0x01U 28404 #define POS_LOW_OFFSET 0x03U 28405 #define DEFAULT_OFFSET 0x04U 28406 #define I_ARRAY_SIZE 50U 28464 int16_t i_array [ 50U ] ;
28473 uint16_t v_array [ 50 ] ;
28609 #include "../system_definitions.h" 28638 int8_t v_adj [ 1 ] ;
28654 uint16_t current_array [ 5 ] ;
28859 #include "../system_config.h" 28860 #include "../system_definitions.h" 28905 uint8_t null_count ;
28906 bool send_message_complete_flag ;
28913 uint8_t table_count ;
28925 uint8_t byte [ 4 ] ;
28945 uint8_t identifier ;
28947 uint8_t msg_length ;
28948 uint8_t xmit_ready_flag ;
29033 static const uint8_t
29035 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
29036 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
29037 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
29038 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
29039 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
29040 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U
29041 , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U ,
29042 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU
29043 , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU ,
29044 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U
29045 , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
29047 static const uint8_t
29049 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
29050 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
29051 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
29052 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
29053 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
29054 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
29090 uint8_t Identifier ,
29092 uint8_t Msg_Length ) ;
29305 #include <stdbool.h> 29306 #include "../system_config.h" 29307 #include "../system_definitions.h" 29323 #define ManHalfUpper 11800U 29324 #define ManHalfLower 2000U 29325 #define ManFullUpper 20000U 29326 #define ManFullLower 11801U 29327 #define NoManBits 32U 29328 #define HalfBit 0x12U 29329 #define FullBit 0x10U 29330 #define SizeOfBiasLUT 48U 29410 uint16_t preamble [ 5 ] ;
29411 uint16_t time [ 96 ] ;
29412 uint8_t level [ 96 ] ;
29413 uint8_t ans [ 32U + 2 ] ;
29414 uint8_t msg [ 4 ] ;
29448 uint16_t adj [ 1 ] ;
29840 #include <stdbool.h> 29841 #include <stdint.h> 29847 #define FIFO_RX_SIZE 7 29848 #define FIFO_TX_SIZE 7 29850 #define FIFO_ADD_OK 0 29851 #define FIFO_FULL 1 29853 #define FIFO_EMPTY 2U 29864 uint8_t * ptr_buffer ;
29869 uint8_t num_records ;
29870 uint8_t put_error ;
29871 uint8_t get_error ;
29912 uint8_t * ptrBuffer ,
29913 uint16_t Length ) ;
30000 TFifo * ptrFifo ) ;
30025 TFifo * ptrFifo ) ;
30057 #include <stdbool.h> 30058 #include <stdint.h> 30099 uint8_t command [ 7 ] ;
30100 bool process_complete_flag ;
30101 bool b_command_complete_flag ;
30102 bool sw_status_bit_check ;
30337 #include <stdint.h> 30338 #include <stdbool.h> 30339 #include "../system_config.h" 30340 #include "../system_definitions.h" 30453 #include <stdint.h> 30454 #include <stdbool.h> 30455 #include <stddef.h> 30456 #include <stdlib.h> 30457 #include "system_config.h" 30458 #include "system_definitions.h" 30609 #include "../system_definitions.h" 30777 #include "../system_config.h" 30778 #include "../system_definitions.h" 30779 #include <stdbool.h> 30785 #define I_ARRAY_SIZE 50U 30830 uint16_t voltage_limit ;
30831 uint16_t upper_voltage_limit ;
30832 uint16_t volt_count ;
30834 uint16_t max_current ;
30835 uint16_t current_limit ;
30836 uint16_t upper_current_limit ;
30837 uint8_t over_current_count ;
30838 uint8_t array_count ;
30839 int16_t i_array [ 50U ] ;
30841 bool new_current_values_flag ;
30842 bool new_voltage_values_flag ;
30843 bool overcurrent_flag ;
30844 bool overvoltage_flag ;
30845 uint16_t sensor_offset ;
30846 uint16_t sensor_constant ;
30847 bool sensor_offset_tick ;
30848 uint16_t v_array [ 50 ] ;
30854 uint8_t overvoltage_count ;
30914 #ifndef SYSTEM_OKAY_H 30915 #define SYSTEM_OKAY_H 30921 #include <stdint.h> 30922 #include <stdbool.h> 31034 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
31070 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 30)));
31091 #define qqqbranches 64 31092 #define QQQMAXMCDCSIZE 2 31096 #define ldra_sscanf 31112 #undef qqnull_params 31113 #define qqnull_params void 31115 #define qqzzidfield 1 31121 #define QQQFIXEDSIZE 31141 qqcptr = qqscan_str;
31143 while (qqcptr[0] ==
' ')
31149 if (qqcptr[0] ==
'-')
31155 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
31157 qqvalue = 10 * qqvalue;
31158 qqvalue = qqvalue + (qqcptr[0] -
'0');
31161 qqvalue = qqisign * qqvalue;
31187 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
31188 ldra_port_write (&ldra_buffer[0]);
31196 ldra_port_write(s);
31204 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
31205 ldra_port_write (&ldra_buffer[0]);
31213 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
31214 ldra_port_write (&ldra_buffer[0]);
31222 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
31223 ldra_port_write (&ldra_buffer[0]);
31342 static int branches_printed = 0;
31346 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
31347 ldra_port_write (&ldra_buffer[0]);
31348 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
31349 ldra_port_write (&ldra_buffer[0]);
31351 branches_printed += 8;
31371 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 31372 #define LASTELEMENT 31373 #include "app_64zbelem.def"
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
static void qqoutput(FILEPOINT char *s, int i)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
#define DRV_IC_Open(drvIndex, intent)
void DRV_TMR1_CounterValueSet(uint32_t value)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
static void DRV_TMR4_Tasks(void)
static int app_64zqendz(int qqqi)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
static float32_t Calc_Fsk_Scaling(void)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void DRV_TMR2_CounterValueSet(uint32_t value)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void Calc_Auto_Bias(void)
static void Init_WL_CPS(void)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void SYS_DEBUG_Message(const char *message)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
uint8_t Fifo_Put(TFifo *ptrFifo, uint8_t Data)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_TMR2_Initialize(void)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
uint8_t Fifo_Get(TFifo *ptrFifo)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
uint8_t DRV_USART0_ReadByte(void)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_BAUD_SET_RESULT
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
static void store_switches(void)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool Valid_Command(uchar8_t msg)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
static const uint8_t Xmit11[312]
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void WriteUART(void)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
static void qqqbitmapreset(qqnull_params)
void DRV_TMR3_CounterValueSet(uint32_t value)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
void DRV_ADC0_Close(void)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
uintptr_t DRV_SPI_BUFFER_HANDLE
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR_Close(DRV_HANDLE handle)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
uint32_t DRV_TMR4_CounterValueGet(void)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
uint8_t timer1_1000mS_count
bool SYS_DMA_IsBusy(void)
void DRV_TMR3_StopInIdleEnable(void)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
uint8_t overvoltage_count
static void Send_Message_Tasks(void)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
static void ReadUART(void)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool DRV_TMR2_Start(void)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
void Set_HVPS_Ramp_Rate(uint16_t value)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
uint8_t upper_current_limit
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void Adjust_WL_CPS_Voltage(uint8_t target)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
DRV_USART_BAUD_SET_RESULT
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void PLIB_USART_Enable(USART_MODULE_ID index)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR2_Status(void)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
uint8_t jobQueueReserveSize
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
bool DRV_TMR1_Start(void)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_MODULE_INIT moduleInit
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
static void read_switches(void)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
static const uint8_t Xmit00[168]
uint8_t DRV_PMP0_Read(void)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
void DRV_IC0_Initialize(void)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
static int qqqisinitialised
DRV_USART_TRANSFER_STATUS
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
bool DRV_USART0_TransmitBufferIsFull(void)
bool spi_write_complete_flag
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_PMP0_ModeConfig(void)
static SYS_STATUS DRV_TMR0_Status(void)
uint32_t DRV_TMR2_CounterValueGet(void)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void DRV_TMR_Stop(DRV_HANDLE handle)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
uint8_t over_current_count
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
INT_SOURCE txInterruptSource
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
static void Execute_System(void)
void PLIB_USART_Disable(USART_MODULE_ID index)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
static bool Check_Manchester(void)
void DRV_TMR1_PeriodValueSet(uint32_t value)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_CHAIN_PRIO
void DRV_TMR3_Initialize(void)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
uint32_t DRV_TMR0_CounterValueGet(void)
void DRV_TMR2_CounterClear(void)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Test_Manchester(void)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void APP_Initialize(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
static void Send_Mark(void)
DRV_USART_TRANSFER_STATUS
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
static void MAN_PROCESS_Tasks(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool DRV_TMR_Start(DRV_HANDLE handle)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
ldra_void_function qqqaccumupload[QQQnumfil]
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SPI_FRAME_PULSE_WIDTH framePulseWidth
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
bool spi_write_complete_flag
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR3_StopInIdleDisable(void)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static SYS_STATUS DRV_TMR4_Status(void)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
USB_ENDPOINT_ADDRESS endpointTx
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
static void DRV_TMR0_Close(void)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
void DRV_TMR1_StopInIdleEnable(void)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
void Set_WL_SPS_CurrentLimit(uint16_t value)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
static void DRV_TMR2_DeInitialize(void)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
static void qqqupload(qqnull_params)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
void SYS_DEBUG_Print(const char *format,...)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void Generate_Sine_Wave_Data(float32_t NoOfTicks)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Execute_Protocol_A(void)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void DRV_TMR1_StopInIdleDisable(void)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
uint16_t DRV_IC0_Capture16BitDataRead(void)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void DRV_TMR3_CounterClear(void)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
SYSTEM_OKAY_DATA SYSTEM_OKAY
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
USB_DEVICE_TRANSFER_HANDLE writeTranferHandle
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR3_CounterValueGet(void)
USB_DEVICE_HANDLE usbDevHandle
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
void DRV_TMR4_CounterValueSet(uint32_t value)
static void DRV_TMR1_Close(void)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void qqqtotalupload(void)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
bool DRV_SPIn_ReceiverBufferIsFull(void)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t Fifo_Length(TFifo *ptrFifo)
uint32_t DRV_TMR0_PeriodValueGet(void)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
static void process_switches(void)
void DRV_TMR0_StopInIdleEnable(void)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
static SYS_STATUS DRV_TMR3_Status(void)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
void DRV_TMR0_Initialize(void)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
static SYS_STATUS DRV_TMR1_Status(void)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void usb_watchdog(void)
DRV_SPI_BUFFER_HANDLE bufferHandle2
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
static void execute_switches(void)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void DRV_ADC_Initialize(void)
static void DRV_TMR1_Open(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void DRV_USART0_WriteByte(const uint8_t byte)
bool process_complete_flag
void DRV_USART0_Deinitialize(void)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void DRV_TMR0_PeriodValueSet(uint32_t value)
static void DRV_TMR2_Close(void)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
static void Send_Space(void)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
CLK_BUSES_PERIPHERAL spiClk
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
USB_DEVICE_TRANSFER_HANDLE readTranferHandle
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
static void DRV_TMR1_Tasks(void)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
SPI_COMMUNICATION_WIDTH commWidth
SYS_DMA_CHANNEL_IGNORE_MATCH
uint32_t DRV_IC0_Capture32BitDataRead(void)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
static void DRV_TMR2_Open(void)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
#define DRV_IC_Close(handle)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void DRV_TMR0_CounterValueSet(uint32_t value)
void DRV_TMR2_StopInIdleDisable(void)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
static void Package_Manchester(void)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
uint16_t upper_current_limit
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DMA_Resume(void)
void DRV_TMR1_Initialize(void)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void DRV_USART0_Close(void)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
static int app_64zscanf(char *qqscan_str)
uint16_t upper_voltage_limit
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
void(* ldra_void_function)()
uint8_t timer1_10mS_count
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
void DRV_TMR0_CounterClear(void)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void SYSTEM_OKAY_Tasks(void)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
uint8_t dump_fire_switch_S7
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
static void DRV_TMR0_Tasks(void)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void DRV_TMR4_CounterClear(void)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
uint8_t timer1_100mS_count
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
static void Execute_Auto_Protocol_A(void)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR3_PeriodValueSet(uint32_t value)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_PMP0_Initialize(void)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
static int qqqstructzzopen
void DRV_TMR2_StopInIdleEnable(void)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
float32_t current_constant
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void DRV_TMR4_Initialize(void)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
struct _DRV_SPI_INIT DRV_SPI_INIT
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void Set_Bias(uint8_t value)
static void DRV_TMR1_DeInitialize(void)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool DRV_TMR4_Start(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uint32_t DRV_TMR1_CounterValueGet(void)
static int qqqqbmselwidth
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
bool new_current_values_flag
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool new_voltage_values_flag
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
uintptr_t DRV_USART_BUFFER_HANDLE
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
static void DRV_TMR3_Open(void)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
MAN_PROCESS_STATES Process_state
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void DRV_TMR4_PeriodValueSet(uint32_t value)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
void SYS_PORTS_Initialize()
void DRV_USART_Close(const DRV_HANDLE handle)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
uint8_t overvoltage_count
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
static void Flush_Buffer_Manchester(void)
void SET_WL_SPS_IOffset(uint8_t mode)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void DRV_ADC1_Close(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void Fifo_Init(TFifo *ptrFifo, uint8_t *ptrBuffer, uint16_t Length)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
USB_ENDPOINT_ADDRESS endpointRx
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_Suspend(void)
SPI_AUDIO_PROTOCOL audioProtocolMode
void DRV_ADC_DeInitialize(void)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
DRV_SPI_CLOCK_MODE clockMode
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
static void DRV_TMR4_Close(void)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle2
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void qqoutput2(FILEPOINT char *s, int i, int j)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void DRV_PMP0_Write(uint8_t data)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
static unsigned char qqqzzglobflag
static int app_64zqzqzq(int qqqi)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool GetDepthStatus(void)
void DRV_USART0_TasksError(void)
INT_SOURCE rxInterruptSource
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
void DRV_TMR4_StopInIdleEnable(void)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
static void qqqqinitialise(int ii)
static void Init_FSK(void)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
uint8_t over_current_count
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void Set_WL_CPS_CurrentLimit(uint8_t value)
static void Init_Manchester(void)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
INT_SOURCE errInterruptSource
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
ldra_void_function qqqaccumreset[QQQnumfil]
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
static void DRV_TMR3_Close(void)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool DRV_TMR3_Start(void)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static int app_64zqqzqz(qqnull_params)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
uint32_t DRV_TMR1_PeriodValueGet(void)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
static void DRV_TMR3_Tasks(void)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
static void Decode_Manchester(void)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
uint8_t timer1_100uS_count
void Prepare_Dwn_Msg(uint8_t Identifier, uint8_t Cmd, uint8_t Msg_Length)
uint32_t DRV_TMR4_PeriodValueGet(void)
static void DRV_TMR4_Open(void)
bool DRV_IC0_BufferIsEmpty(void)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void DRV_TMR4_StopInIdleDisable(void)
DRV_SPI_TASK_MODE taskMode
void DRV_USART0_TasksTransmit(void)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
bool DRV_TMR0_Start(void)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_ERROR_LEVEL gblErrLvl
static void DRV_TMR0_Open(void)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
static void Read_WL_CPS_V_I(void)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
static void DRV_TMR3_DeInitialize(void)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
static void Execute_Protocol_B(void)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
SPI_FRAME_SYNC_PULSE frameSyncPulse
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
static void DRV_TMR0_DeInitialize(void)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
static void Check_WL_CPS_Over_Current(void)
static void ValidateComm(void)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)